Design verification has traditionally been second tier to design creation. Early on, a majority of a design cycle was spent on the creation of a design. Verification was performed on an “as needed” basis and typically only for critical portions of a design; verification was rarely performed on a complete design. Design verification was resultantly a small portion of a project's time and finance budget. As a result of a number of factors, it became apparent that more effort was need on the verification portion of a product development cycle.
Concurrent with this realization of the need for greater verification efforts in product development cycles, great strides were being made in efficiency of the design portion of the cycle through paradigm shifts. Unfortunately, while the realization of the need for verification arrived, the verification paradigm did not make the same strides in efficiency as did the design paradigm.
The verification approach to designs involved several methods. One was a brute force, exercise all pins method. This approach involves exercising every combination of inputs to a design and observing the outputs. This approach has several drawbacks. First, it requires 2 to the n vectors, where n is the number of input pins. Second, it does not take into account state behavior of the device. Third, it will likely result in redundant testing of some portion of the design.
A second solution was to write custom models for testing, at least portions of, devices under verification. This, however, also has drawbacks. First, this solution requires knowledge of details of the implementation down to the pin level. Second, it may result in duplicated efforts when a design reuses portions of an existing design.
What has resulted from these solutions is a typical design scenario where the verification resources are reaching 70% of the total project resource pool. What is desired is a more efficient verification approach.